- clock recovery loop
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схема восстановления тактовой частоты
Англо-русский словарь технических терминов. 2005.
clock recovery loop
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Clock recovery — Some digital data streams, especially high speed serial data streams (such as the raw stream of data from the magnetic head of a disk drive) are sent without an accompanying clock signal. The receiver generates a clock from an approximate… … Wikipedia
Clock Recovery — Die Taktrückgewinnung (auch Symboltakt Synchronisation) in der digitalen Übertragungstechnik hat zum Ziel, aus einem empfangenen Digitalsignal den Sendetakt des Senders zu bestimmen und damit das zeitgenaue Abtasten des Empfangsignals zu… … Deutsch Wikipedia
Phase-locked loop — PLL redirects here. For other uses, see PLL (disambiguation). A phase locked loop or phase lock loop (PLL) is a control system that generates an output signal whose phase is related to the phase of an input reference signal. It is an electronic… … Wikipedia
Delay-locked loop — In electronics, a delay locked loop (DLL) is a digital circuit similar to a phase locked loop (PLL), with the main difference being the absence of an internal voltage controlled oscillator. A DLL can be used to change the phase of a clock signal… … Wikipedia
Jitter — For other meanings of this word, see Jitter (disambiguation). Jitter is the undesired deviation from true periodicity of an assumed periodic signal in electronics and telecommunications, often in relation to a reference clock source. Jitter may… … Wikipedia
Injection locking — is a high frequency (usually RF, but possibly microwave and optical) phenomenon where an oscillator directly synchronizes to another high frequency signal. In the case of a VCO an injection locking signal may override its low frequency control… … Wikipedia
Mercury-Redstone 4 — Mission insignia Mission statistics Mission name Mercury Redstone 4 Spacecraft name Liberty Bell 7 Spacecraft mass 1,286 … Wikipedia
SerDes — A Serializer/Deserializer (SerDes pronounced sir deez) is a pair of functional blocks commonly used in high speed communications to compensate for limited input/output. These blocks convert data between serial data and parallel interfaces in each … Wikipedia
Phase detector — A phase detector is a frequency mixer or analog multiplier circuit that generates a voltage signal which represents the difference in phase between two signal inputs. It is an essential element of the phase locked loop (PLL).Detecting phase… … Wikipedia
MPEG-2 — Not to be confused with MPEG 1 Audio Layer II (MP2). MPEG 2 is used in Digital Video Broadcast and Digital Versatile Discs. The MPEG transport stream, TS, and MPEG program stream, PS, are container formats. MPEG 2 is a standard for the generic… … Wikipedia
8b/10b encoding — In telecommunications, 8b/10b is a line code that maps 8 bit symbols to 10 bit symbols to achieve DC balance (see DC coefficient) and bounded disparity, and yet provide enough state changes to allow reasonable clock recovery. This means that the… … Wikipedia
