processor pipeline
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pipeline processor — srautinis procesorius statusas T sritis automatika atitikmenys: angl. pipeline processor; pipelined processor vok. Pipeline Prozessor, m rus. конвейерный процессор, m; процессор поточной обработки, m pranc. processeur à chaîne de production, m;… … Automatikos terminų žodynas
Processor register — In computer architecture, a processor register is a small amount of storage available as part of a CPU or other digital processor. Such registers are (typically) addressed by mechanisms other than main memory and can be accessed more quickly.… … Wikipedia
Pipeline-Prozessor — srautinis procesorius statusas T sritis automatika atitikmenys: angl. pipeline processor; pipelined processor vok. Pipeline Prozessor, m rus. конвейерный процессор, m; процессор поточной обработки, m pranc. processeur à chaîne de production, m;… … Automatikos terminų žodynas
Processor Local Bus — Le Processor Local Bus (PLB) est un bus introduit[Quand ?] par IBM dans le cadre de l architecture de bus CoreConnect, qui comprend également les bus OPB (On chip Peripheral Bus) et DCR (Device Control Register). Caractéristiques du bus… … Wikipédia en Français
pipeline — A mechanism used in microprocessors that speeds up the processing of instructions. The Intel Pentium processor features two pipelines, one for data and one for instructions, and can process two instructions per clock cycle. A processor with … Dictionary of networking
Instruction pipeline — Pipelining redirects here. For HTTP pipelining, see HTTP pipelining. Basic five stage pipeline in a RISC machine (IF = Instruction Fetch, ID = Instruction Decode, EX = Execute, MEM = Memory access, WB = Register write back). In the fourth clock… … Wikipedia
Classic RISC pipeline — In the history of computer hardware, some early reduced instruction set computer central processing units (RISC CPUs) used a very similar architectural solution, now called a classic RISC pipeline. Those CPUs were: MIPS, SPARC, Motorola 88000,… … Wikipedia
Vector processor — A vector processor, or array processor, is a CPU design where the instruction set includes operations that can perform mathematical operations on multiple data elements simultaneously. This is in contrast to a scalar processor which handles one… … Wikipedia
Pixel pipeline — The pixel pipeline was a component within 3D accelerators, most prominently prior to DirectX 9. The term encompasses one of a number of parallel processing pipelines within a graphics processing unit (GPU). Each pipeline processes pixel, texture … Wikipedia
Heterogeneous Element Processor — The Heterogeneous Element Processor (HEP) was introduced by Denelcor in 1982 as the world s first commercial MIMD computer. A HEP system, as the name implies, was pieced together from many heterogeneous components processors, data memory modules … Wikipedia
Barrel processor — A barrel processor is a CPU that switches between threads of execution on every cycle. This CPU design technique is also known as interleaved or fine grained temporal multithreading. As opposed to simultaneous multithreading in modern superscalar … Wikipedia